The present disclosure relates to delay circuits used in semiconductor integrated circuits, and more particularly, to techniques of reducing fluctuations in delay time of delay circuits caused by variations in transistor characteristics.
In recent years, as semiconductor microfabrication technology has progressed, variations in characteristics of transistors etc. included in semiconductor integrated circuits have increased.
Conventionally, Japanese Patent Publication No. 2003-218239 describes an example delay circuit provided in an SRAM including a sense amplifier drive circuit (ibid, FIG. 1). The delay circuit includes a plurality of delay inverters (ibid, FIG. 9) which are connected in series. In each delay inverter, the overall beta ratio (the ratio of the width to the entire length) of a plurality of NMOS transistors is equal to the beta ratio of a pass transistor (equivalent to an “access transistor” described herein) in a bit cell (equivalent to a “memory cell” described herein). As a result, the delay circuit has the good ability to follow changes in the voltage, temperature, etc. of the bit cell.
However, in Japanese Patent Publication No. 2003-218239, only fluctuations in characteristics of the NMOS transistor which is the pass transistor of the bit cell are taken into consideration, and fluctuations in the delay time of the delay inverter caused by fluctuations in characteristics of the PMOS transistor included in the delay inverter (ibid, FIG. 9) is not taken into consideration.
Fluctuations in transistor characteristics occur in the PMOS transistor as well as the NMOS transistor. In actual devices, some finished transistors have low or high performance, i.e., there are variations in transistor characteristics.
For the delay inverter (delay circuit) of Japanese Patent Publication No. 2003-218239, only fluctuations in characteristics of the NMOS transistor are taken into consideration. Therefore, there is a difference in the delay time of the delay inverter between when the performance of the NMOS transistor is low and the performance of the PMOS transistor is high (condition 1) and when the performance of the NMOS transistor is low and the performance of the PMOS transistor is also low (condition 2).
For example, when data read from a memory cell in an SRAM is amplified by a sense amplifier, a delay circuit is used as a timing generator which generates timing signals for activating a word line, activation of a sense amplifier, etc. In the delay circuit of Japanese Patent Publication No. 2003-218239, the delay time is determined based on characteristics of both the NMOS transistor and the PMOS transistor. Therefore, it is clear that the delay time of the delay circuit under the condition 2 is longer than the delay time of the delay circuit under the condition 1.
In contrast to this, the speed at which data is read from an SRAM memory cell is determined by only the NMOS transistor (the access transistor and the drive transistor), and is not affected by the characteristics of the PMOS transistor. Therefore, the read speed does not change regardless of whether the finished NMOS and PMOS transistors satisfy the condition 1 or the condition 2.
The timing of activation of the sense amplifier is designed so that the sense amplifier can normally amplify data even under the condition 1 which causes the delay time of the delay circuit to be shorter. Conversely, the access time of the SRAM is determined by the condition 2 which causes the delay time of the delay circuit to be longer. Therefore, if there is a difference in the delay time of the delay circuit between the conditions 1 and 2 as in Japanese Patent Publication No. 2003-218239, the access time is disadvantageously increased. Moreover, the amount of a charging/discharging current of a non-selected memory cell from/to a bit line increases, disadvantageously leading to an increase in power consumption.